Compenslow
"Compenslow" is a design parameter for gemstone metamaterial on-chip factories
That allows friction to be reduced by many orders of magnitude while
keeping the areal throughput density capacity of constant.
It counterintuitively allows to reduce friction by increasing total internal bearing surface area.
That is because while friction increases linearly with nanomachinery bearing surface area it falls quadratically with nanomachinery speed.
So doing both (area up and speed down) overall what remains is a linear decrease in friction.
YAY!!
Contents
Specification / Units
Compenslow can be specified in:
- total nanomachinery bearing area per factory chip area or – unit: (m²/m²)
- areal throughput density per absolute nanomachinery speed – unit: ((m³/s)/m²)/(m/s)
The two should be inter-convertible by a design dependent constant.
The reason why it is (to a degree) affordable to increase the amount of nanomachinery by orders of magnitude is:
Higher throughput of smaller machinery
What if the speeds are not slowed down but just the amount of nanomachinery gets increased
Obviously this will need lots of active cooling.
Filling a macroscopic volume to the brim with nanomachinery while keeping absolute speeds constant
would lead to totally impractically high throughput-densities. A hard bottleneck.
Assembly would be so rapid that resource resupply and product removal (the transport motions) would require impossibly high speeds.
For laughs see: Hyper high throughput microcomponent recomposition
Practical devices look differently.
Choice of name
This was just an ad-hoc decision in 2021.
"Compenslow" is a portmanteau for "by more nanomachinery compensated deliberate slowdown".
Math
Absolute throughput for a single stacked column of assembly chambers:
[math] T = n V (v_A/(B^3sFC)) = v_T/(sF) [/math]
(See: Limits to higher throughput of smaller machinery)
[math] T/v_A = n V /(B^3sFC) [/math]
- C is accounting for the how much a single assembly operation deviates from the length sF
- B … branching factor
- F … chamber to part size ratio
But we want throughput per chip area
[math] T' = T/A_{chip} [/math]
so we need the chip area per column:
[math] A_{chip} = (sF)^2 D[/math]
- D … accounts for additional chip area needed for transport channels and other stuff
[math] T'/v_A = n V /(B^3 (sF)C (sF)^2 D) [/math]
With the definition of the product volume:
[math] V = s^3 [/math]
we finally get:
[math] T'/v_A = n /(B^3 F^3 C D) [/math]
(wiki-TODO: Re-check that result, something seems off)
(TODO: Get the compenslow form of "bearing area per factory chip area" formalized too.)
