Compute architectures

This article is a stub. It needs to be expanded.

1 Delineation
2 Mainstream
3 Dedicated compute hardware specifically designed for pure functional languages (lambda calculus)
- 3.1 Term normalization by parallel asynchronous term rewriting
- 3.2 Older works - lambda calculus evaluating hardware
4 Green arrays (related to stack based programming)
- 4.1 Green Arrays Bootstrapping Process
5 Reconfigurable Asynchronous Logic Automata (RALA)
6 Systolic arrays
7 Cellular automata
8 Reversible computing architectures
9 Misc
10 External links

Delineation

This page is about compute architectures aimed for physical (on silicon) implementation.
This page is not about various exotic computing substrates (not: Compute substrates like https://en.wikipedia.org/wiki/Unconventional_computing )
This page is not about purely theoretical machines with no means of mapping them to an on chip design.
Although the lines can blur a bit on that.

Mainstream

There's plenty of resources out on the web so not much details here.

Von Neumann architecture (today's 2024 CPUs)
– Issues here are the enforced serial nature of data processing and the "von Neumann bottleneck".
Graphical Processing Units (GPUs still highly specialized on triangle processing, but changing as of 2024)
FPGAs (Field Programmable Gate Arrays)
Emerging: NPUs & TPUs (for AI) – (not yet more general neuromorphic computing)

Dedicated compute hardware specifically designed for pure functional languages (lambda calculus)

Term normalization by parallel asynchronous term rewriting

Landing page: https://higherorderco.com/
Code: https://github.com/HigherOrderCO
Virtual machine: https://github.com/HigherOrderCO/HVM
Associated proglang: https://github.com/HigherOrderCO/Bend

Older works - lambda calculus evaluating hardware

https://en.wikipedia.org/wiki/SECD_machine
The letters stand for Stack, Environment, Control, Dump—the internal registers of the machine.
https://en.wikipedia.org/wiki/CEK_Machine (based on SECD)

(wiki-TODO: Add details (SECD))

Green arrays (related to stack based programming)

Compared to systolic arrays:

Scale and generality: Green Arrays nodes are more general-purpose and typically deployed at a larger scale on a single chip.
Asynchronous vs. synchronous: Green Arrays operates asynchronously, while systolic arrays are typically synchronous.
Programming model: Green Arrays uses a Forth-inspired model, which is quite different from the typically fixed-function nature of systolic arrays.
Data flow: Systolic arrays have a more rigid, predetermined data flow, while Green Arrays allows for more flexible data movement between nodes.
Application scope: Systolic arrays are often optimized for specific algorithms, while Green Arrays aim for broader applicability.

Green Arrays Bootstrapping Process

Initial State:
The chip starts with one active node (often called the "boot node").
All other nodes are in a dormant or unconfigured state.

Propagation:
The boot node begins by configuring its immediate neighbors.
It loads them with basic functionality, essentially "waking them up".

Cascading Configuration:
The newly configured nodes then participate in configuring their own neighbors.
This process cascades across the chip, with each node potentially configuring others.

Dynamic Programming:
As the configuration spreads, nodes can be programmed with different functionalities.
This allows the chip to configure itself for various tasks dynamically.

Adaptive Behavior:
The configuration process can adapt based on the task at hand or the state of the chip.
This allows for efficient use of resources and fault tolerance.

Collective Intelligence:
The end result is a chip where the collective behavior emerges from the interaction of many simple, individually programmed nodes.

Reconfigurable Asynchronous Logic Automata (RALA)

A physical computing that aims to match to the 3D spacial constraints of our real world.
By Neil Gershenfeld (MIT Center of Bits and Atoms)
(wiki-TODO: Add more details eventually.)

Systolic arrays

https://en.wikipedia.org/wiki/Systolic_array

(wiki-TODO: Add details)

Cellular automata

These are usually not seen as practical general purpose compute architectures.
While some are Turing complete (e.g. Conways game of life)
they seem not particularly suitable/practical for general purpose computations.

Typically they feature simple rules per cell. Thus expressive capabilities are limited.
But they feature complex emergent behaviour which is making them interesting to study.
Obviously they are limited to 3D lattices in physical implementations.

Reversible computing architectures

RevComp - The Reversible and Quantum Computing Research Group Pendulum fist fully adiabatic CPU

2009/2010 – Reversible computer hardware – Alexis De Vos (Ghent university)
https://www.sciencedirect.com/science/article/pii/S1571066110000162
https://lib.ugent.be/en/catalog/pug01:835180 (Ghent University Library)
https://hes.elis.ugent.be/about.html (Ghent University – Hardware and Embedded Systems Group)

Program Inversion and Reversible Computation (landing page)
Janus: a reversible imperative programming language
https://di.ku.dk/english/research/groups/program-inversion-and-reversible-computing/

Reversible (low level) computer software matching the hardware:
Programming Languages and Theory of Computing – Robert Glück
https://research.ku.dk/search/result/?pure=en%2Fpersons%2Frobert-gluck(4a63cb84-71dd-4cf5-a00f-4697b6d4ea17).html
Video about collaboration: https://topps.diku.dk/micropower/MicroPower_Eng_1280x720.mp4
https://server.complang.tuwien.ac.at/talks/Glueck2007-11-09
Papers: https://www.researchgate.net/scientific-contributions/Robert-Glueck-70890035
Papers: https://www.semanticscholar.org/author/R.-Gl%C3%BCck/1700006

2012 – A Reversible Processor Architecture and Its Reversible Logic Design
https://www.researchgate.net/publication/260749482_A_Reversible_Processor_Architecture_and_Its_Reversible_Logic_Design
2007 – Reversible Machine Code and Its Abstract Processor Architecture
https://link.springer.com/chapter/10.1007/978-3-540-74510-5_9

Misc

https://en.wikipedia.org/wiki/Transport_triggered_architecture

Manchester Dataflow Machine, 1980s.
https://steveloughran.blogspot.com/2015/06/the-manchester-dataflow-machine-obscure.html

1980 – SKIM - The S, K, I reduction machine
https://dl.acm.org/doi/10.1145/800087.802798

1082 – Wavefront Array Processor: Language, Architecture, and Applications
https://ieeexplore.ieee.org/document/1675922
(subset of systolic arrays)
Wikipedia: "… Like SIMD machines, clocked systolic arrays compute in "lock-step" with each processor undertaking alternate compute | communicate phases. But systolic arrays with asynchronous handshake between DPUs are called wavefront arrays. …"

1985 – Grip: a parallel graph reduction machine – Simon Loftus Peyton Jones
https://www.researchgate.net/publication/242640459_Grip_a_parallel_graph_reduction_machine

1990 – Executing a Program on the MIT Tagged-Token Dataflow Architecture
https://pages.cs.wisc.edu/~isca2005/ttda.pdf
https://en.wikipedia.org/wiki/Dataflow_architecture

2002 – Executing a program on the MIT tagged-token dataflow architecture
https://ieeexplore.ieee.org/document/48862