Difference between revisions of "Mechanical computation"

Revision as of 15:08, 29 July 2014

mechanical differentials (that includes planetary gear assemblies and linear versions) correspond to simple electrical connections (solder points) the angular speed (corresponding to electrical current) distributes proportional to the loads.

Mechanical logical gates can either be elements that form instantaneous chains or elements that must be by a testing clock signal.

With a single type of universal logical gate any 'programmable logic arrays' (PLA) can be made by putting many of them together in disjunctive or conjunctive normal form (DNF / CNF)

Reversible mechanical logic

Reversible mechanics means: whenever an elastic element (a spring) is de-tensioned it must feed back its stored energy into the energy source.

Testing a clocked reversible mechanical gate is done via pulling pushing turning twisting or whatever against a potential steric hindrance obstacle that was put in place (or not) by the precedent gate . As long as the outputs are in use the inputs cannot be removed. If they would be removed all consecutive outputs would snap back - BAD. Thus the testing clock signal must rise like a bar graph display.

This is best done till an appropriate computation result is reached that has way viewer bits than the intermediate computation steps that lead there. This result can then be copied into a storage register and the output deleted. Meaning a view testing springs snap back irreversible and release their energy into the background heat bath.

Finally one let the bar graph clock signal stepwisely recede letting go of the testing gates in reverse order and pushing back the energy into the energy source (e.g. a flywheel). One could say one un-computes the intermediate data garbage.

This hole process is called a retractile cascade

The energy swings back and forth between the energy storage and the many logic gates. Tree like distributed though mechanical differenials.

In a programmable logic array (PLA) first the gates in the AND-plane and then the gates in the OR-plane must be evaluated in sequence. The results may be fed back into other yet unevaluated parts of the PLA for a second and further rounds.

concrete implementations

• rod logic
• rotative logic
• pure flexture logic
• ...

analogous usage