View source for Compute architectures

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== Mainstream ==

'''There's plenty of resources out on the web so not much details here.'''
* Von Neumann architecture (today's 2024 CPUs) <br>– Issues here are the enforced serial nature of data processing and the "von Neumann bottleneck". 
* Graphical Processing Units (GPUs still highly specialized on triangle processing, but changing as of 2024)
* FPGAs (Field Programmable Gate Arrays)
* Emerging: NPUs & TPUs (for AI) – (not yet more general neuromorphic computing)

== Reconfigurable Asynchronous Logic Automata (RALA) ==

A physical computing that aims to match to the 3D spacial constraints of our real world. <br>
{{wikitodo|Add details}}

== Green arrays ==

'''Compared to systolic arrays:'''
* '''Scale and generality:''' Green Arrays nodes are more general-purpose and typically deployed at a larger scale on a single chip.
* '''Asynchronous vs. synchronous:''' Green Arrays operates asynchronously, while systolic arrays are typically synchronous.
* '''Programming model:''' Green Arrays uses a Forth-inspired model, which is quite different from the typically fixed-function nature of systolic arrays.
* '''Data flow:''' Systolic arrays have a more rigid, predetermined data flow, while Green Arrays allows for more flexible data movement between nodes.
* '''Application scope:''' Systolic arrays are often optimized for specific algorithms, while Green Arrays aim for broader applicability.

=== Green Arrays Bootstrapping Process ===

'''Initial State:''' <br>
The chip starts with one active node (often called the "boot node"). <br>
All other nodes are in a dormant or unconfigured state. <br>

'''Propagation:''' <br>
The boot node begins by configuring its immediate neighbors. <br>
It loads them with basic functionality, essentially "waking them up". <br>

'''Cascading Configuration:''' <br>
The newly configured nodes then participate in configuring their own neighbors. <br>
This process cascades across the chip, with each node potentially configuring others. <br>

'''Dynamic Programming:''' <br>
As the configuration spreads, nodes can be programmed with different functionalities. <br>
This allows the chip to configure itself for various tasks dynamically. <br>

'''Adaptive Behavior:'''  <br>
The configuration process can adapt based on the task at hand or the state of the chip. <br>
This allows for efficient use of resources and fault tolerance. <br>

'''Collective Intelligence:''' <br>
The end result is a chip where the collective behavior emerges from the interaction of many simple, individually programmed nodes. <br>

== Systolic arrays ==

{{wikitodo|Add details}}

== Cellular automata ==

These are usually not seen as practical general purpose compute architectures. <br>
While some are Turing complete (e.g. Conways game of life) <br>
they seem not particularly suitable/practical for general purpose computations. <br>

Typically they feature simple rules per cell. Thus expressive capabilities are limited. <br> 
But they feature complex emergent behaviour which is making them interesting to study. <br>
Obviously they are limited to 3D lattices in physical implementations.

== Machines specifically designed for pure functional languages (lambda calculus) ==

{{wikitodo|Add details (SECD)}}

== Reversible computing architectures ==

{{wikitodo|Add details (pendulum)}}

== External links ==

* https://en.wikipedia.org/wiki/Computer_architecture
* https://en.wikipedia.org/wiki/Von_Neumann_architecture (mainstream till today)
* https://en.wikipedia.org/wiki/Von_Neumann_architecture#von_Neumann_bottleneck (a big issue with it)
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* 2010 RG – [https://www.researchgate.net/publication/220997151_Reconfigurable_Asynchronous_Logic_Automata_RALA Reconfigurable Asynchronous Logic Automata (RALA)] 
* 2010 pdf – [https://fab.cba.mit.edu/classes/865.18/replication/Gershenfeld.pdf Reconfigurable Asynchronous Logic Automata (RALA)]
* 2011 pdf – [https://fab.cba.mit.edu/classes/MAS.862/notes/computation/Gershenfeld-2011.pdf Aligning the representation and reality of computation with asynchronous logic automata – Neil Gershenfeld]
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* Green arrays
* https://en.wikipedia.org/wiki/Systolic_array
* https://en.wikipedia.org/wiki/SECD_machine <br>The letters stand for Stack, Environment, Control, Dump—the internal registers of the machine.
* https://en.wikipedia.org/wiki/CEK_Machine (based on SECD)
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* https://en.wikipedia.org/wiki/Cellular_automaton
* https://en.wikipedia.org/wiki/Elementary_cellular_automaton
* https://en.wikipedia.org/wiki/Conway%27s_Game_of_Life
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* https://en.wikipedia.org/wiki/Petri_net (drifting slightly off-topic)
* https://en.wikipedia.org/wiki/Open_architecture
* https://en.wikipedia.org/wiki/Very-large-scale_integration (VLSI)
* https://en.wikipedia.org/wiki/Neuromorphic_engineering
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* https://en.wikipedia.org/wiki/Fabric_computing
* [[Cross network computing architectures]] (better to cover on other page)
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* https://en.wikipedia.org/wiki/Nondeterministic_constraint_logic
* [https://www.youtube.com/watch?v=ccD0yAk1wL0 MIT OpenCourseWare – 17. Nondeterministic Constraint Logic]